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Preliminary Technical Data
FEATURES
800 MHz Clock Distribution IC, PLL Core, Dividers, Delay Adjust, Five Outputs AD9511
FUNCTIONAL BLOCK DIAGRAM
VS GND RSET CPRSET VCP DISTRIBUTION REF
Low phase noise phase-locked loop core Reference input frequencies to 250 MHz Programmable dual-modulus prescaler Programmable charge pump (CP) current Separate CP supply (VCP) extends tuning range Two 1.5 GHz, differential clock inputs 5 programmable dividers, 1 to 32, all integers Phase select for output-to-output coarse delay adjust 3 independent 800 MHz LVPECL outputs Additive output jitter 225 fs rms 2 independent 800 MHz/250 MHz LVDS/CMOS clock outputs Additive output jitter 275 fs rms Fine delay adjust on 1 output, 6-bit delay word 4-wire or 3-wire serial control port Space-saving, 48-lead LFCSP
AD9511
PHASE
PLL REF
REFIN REFINB
R DIVIDER N DIVIDER
FREQUENCY
DETECTOR
CHARGE PUMP
CP
FUNCTION
SYNCB, RESETB PDB
PLL SETTINGS
STATUS
CLK1 CLK1B PROGRAMMABLE DIVIDERS & PHASE ADJUST LVPECL
CLK2 CLK2B
/1,/2,/3 ... /31,/32
LVPECL
OUT0 OUT0B
/1,/2,/3 ... /31,/32
LVPECL SERIAL CONTROL PORT
OUT1 OUT1B
SCLK SDIO SDO CSB
/1,/2,/3 ... /31,/32
LVDS/CMOS
OUT2 OUT2B
/1,/2,/3 ... /31,/32
OUT3 OUT3B DELAY ADJUST LVDS/CMOS OUT4 OUT4B
APPLICATIONS
Low jitter, low phase noise clock distribution Clocking high speed ADCs, DACs, DDS, DDC, DUC, MxFEs High performance wireless transceivers High performance instrumentation Broadband infrastructure
/1,/2,/3 ... /31,/32
T
Figure 1.
GENERAL DESCRIPTION
The AD9511 provides a multi-output clock distribution function along with an on-chip PLL core. The design emphasizes low jitter and phase noise in order to maximize data converter performance. Other applications with demanding phase noise and jitter requirements also benefit from this part. The PLL section consists of a programmable reference divider (R); a low noise phase frequency detector (PFD); a precision charge pump (CP); and a programmable feedback divider (N). By connecting an external VCXO or VCO to the CLK2/CLK2B pins, frequencies up to 1.5 GHz may be synchronized to the input reference. There are five independent clock outputs. Three outputs are LVPECL, and two are selectable as either LVDS or CMOS levels. The LVPECL and LVDS outputs operate to 800 MHz, and the CMOS outputs operate to 250 MHz.
Each output has a programmable divider that may be bypassed or set to divide by any integer up to 32. The phase of one clock output relative to another clock output may be varied by means of a divider phase select function, which serves as a coarse timing adjustment. One of the LVDS/CMOS outputs also features a programmable delay element with a range of up to 10 ns of delay. This fine tuning delay block has 6-bit resolution, giving 64 possible delays from which to choose. The AD9511 is ideally suited for data converter clocking applications where maximum converter performance is achieved by encode signals with subpicosecond jitter. The AD9511 is available in a 48-lead LFCSP and may be operated from a single 3.3 V supply. An external VCO that requires an extended voltage range may be accommodated by connecting the charge pump supply (VCP) to 5.5 V. The temperature range is -40C to +85C.
Rev. PrA
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 (c) 2004 Analog Devices, Inc. All rights reserved.
AD9511 PIN CONFIGURATION
47 CPRSET 41 OUT0B 45 RSET 42 OUT0 46 GND 43 GND 37 GND 38 GND
Preliminary Technical Data
REFIN REFINB VS VCP CP VS
1 2 3 4 5 6
39 VS
40 VS
48 VS
44 VS
36 VS
pin 1 indicator
35 OUT3 34 OUT3B 33
VS VS
AD9511
Top View (Not to scale) 48-lead LFCSP 7 x 7 x 0.85
32
31 OUT4 30 OUT4B 29 VS 28 VS 27 26 25
OUT1 OUT1B VS
CLK2 7 CLK2B 8 VS CLK1 CLK1B
9 10 11
FUNCTION 12
STATUS 13
SCLK 14
OUT2B 20
OUT2 21
15
SDO 16
17
18
19
22
VS 23
CSB
SDIO
Figure 2.
Note that the exposed paddle on this package is an electrical connection as well as a thermal enhancement. For the device to function properly, the paddle must be attached to ground, GND.
(c) 2004 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective companies.
PR05286-0-11/04(PrA)
Rev. PrA | Page 2 of 2
GND
GND 24
VS
VS
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